Conventionally, in order to make an addition between two binary numbers, a standard adder calculates each bit of the resulting sum from the bits of the same rank of each binary input number, and of a carry propagated by the addition of the bits of lower rank.
In other words, these standard adders effect the sum of the two bits of the rank in question of the two binary input numbers, and then make a positive correction if necessary using the propagated carry.
For example, the U.S. Pat. Nos. 6,175,852 and 5,636,156 (IBM) present this type of adder.
The U.S. Pat. No. 6,578,063 (IBM) also presents a standard adder but with five input binary numbers.
The U.S. Pat. No. 5,719,803 (Hewlett Packard Company) keeps the structure of a standard adder while affording an improvement based on Ling's equations.
One of the drawbacks of this type of adder concerns the testability of the logic gates of the adder. This is because, so as to check the behaviour of the gates, it is necessary to use a set of vector tests in order to detect any error in behaviour of the adder. In the case of these standard adders, the number of vectors in this set of tests may be extremely high.
The article “On the Adders with Minimum Tests” by Seiji Kajihara and Tsutomu Sasao proposes to improve the testability of these standard adders by modifying certain gates but without changing the general structure of the adder.